This invention relates to in-circuit digital testers. More particular, the invention relates to a circuit for generating test signals for testing bus oriented electronic components, such as microprocessors.
As used herein, an in-circuit digital tester refers to a tester that is capable of testing a circuit without regard to whether or not the electrical node into which a test signal is injected is connected to the output of another logic device. In-circuit testers are capable of generating and applying a digital test signal to an output node of a logic device that is normally at a logic ground to cause that output to go to a logic high without damaging the device. In other words, the use of the term "in-circuit" means that the device or circuit under test does not have to be isolated or removed from the surrounding circuits in order to apply test signals and to monitor its output.
Prior-art in-circuit digital testers, such as that disclosed in U.S. Pat. No. 4,216,539 which is assigned to the assignee of the present application, and which is hereinafter incorporated for all purposes, provides a digital test signal generator with each pin in a bed of nails fixture capable of generating a wide variety of digital test signals to test components in a circuit under test. Some components however, require an especially complexed test signal pattern generation in order to adequately test the electrical performance characteristics of the component. One such component is a microprocessor chip. Such components are generally bus oriented devices requiring the generation of multi-lined data bus signals which may represent data or may represent addresses. In addition, to properly exercise or set up a data bus signal generation sequence, a sequence of control signals must precede or be generated concurrently with the data bus signals before the microprocessor can properly execute its internal sequences. Because the microprocessor performs all of its instructions using repeated selected signal sequences, such as an instruction fetch cycle, a read from memory cycle, a write to memory cycle, etc., in order to generate these required complex test signal patterns and to generate them in lengthy patterns, some means must be provided for minimizing the amount of pin memory needed to store the test signal generating data that will be used during the test cycle to generate the required test signal patterns.
To solve the problem of generating these complexed test signal patterns while utilizing the advantages and novelty over the prior-art for in-circuit digital testers offered by the invention disclosed in the application incorporated above, the present invention has segregated the test signals for bus oriented devices into two categories--data bus signals and protocol or control test signals. The data bus signals are applied as parallel words onto the multi-lined data buses, functioning either as data or as addresses. A plurality of individual control signals are generated in timed relationship such that when all the control signals are viewed in parallel, they define a protocol sequence which communicates to a device the necessary information for the device to perform a normally intended function. From these predefined protocol sequences, all of the functions of the device may be exercised by recursively generating the protocol sequences as required to test each function of the device.